Scaling of semiconductor devices is becoming ever more difficult in sub-22 nm technologies. For example, as structures continue to scale downward, via contact resistance becomes a performance limiting factor; that is, the via contact resistance becomes very high, particularly in back end of the line (BEOL) via interconnect structures.
By way of example, dual-damascene fill processes require PVD liner/barrier deposition. Due to the line width requirements in scaled technologies, e.g., sub 22 nm, the liner/barrier deposition will displace the primary conductor. As the PVD liner/barrier materials, e.g., TaN and Ta, have higher resistance than the primary conductors, e.g., Cu, dual-damascene fill processes have become a major contributor to increased contact resistance. This increased contact resistance, in turn, leads to decreased performance of the semiconductor device.
Also, as process technologies continue to shrink towards 14-nanometers (nm) and beyond, it is becoming difficult to build self-aligned fine pitch vias with current lithography processes. This is mainly due to the size of the underlying wiring lines, e.g., width of the underling wiring structure, as well as current capabilities of lithography tool optics for 32 nm and smaller dimension technologies.